1. Field of the Invention
The present invention relates generally to the field of communication devices and more particularly to an improved charge pump-based phase locked loop circuit, usable in a frequency synthesizer.
2. Related Art
Digital communication devices employ frequency synthesizers for controlling transmission and reception frequency for radio communication. Phase locked loops (PLLs) are routinely used for data communications, frequency synthesis, clock generation, clock recovery, and similar applications. PLLs are often implemented in integrated circuits and commonly are realized with charge pump techniques.
FIG. 1 illustrates a block diagram of a conventional charge pump-based phase locked loop circuit. The phase locked loop circuit includes a phase/frequency detector 14, a charge pump 18, a loop filter 20, a voltage-controlled oscillator (VCO) 22, a reference divider 12 and an M divider 24. The basic digital PLL circuit of FIG. 1 receives an input signal 10, in form of binary signals (square waves) with reference frequency f.sub.ref, from a reference frequency source, not shown. The reference frequency source is a crystal oscillator which generates a well-controlled reference signal at a known high frequency. The reference divider 12 divides the input signal 10 reference frequency f.sub.ref by an integer R, to allow use of a higher frequency reference frequency source. In response to this reference signal, the local oscillator VCO 22 generates an output signal 16.
The output signal of the reference divider 12 is an input signal 13 of the phase/frequency detector 14. The PLL circuit output signal 16 with frequency f.sub.out is also input into the phase/frequency detector 14, into its feedback input, after modification in the M divider 24. The phase/frequency detector 14 outputs a signal 19 having a voltage proportional to a phase difference between the frequencies of the two signals input into the phase/frequency detector 14. The output of the phase/frequency detector 14 is coupled to the charge pump 18, the output current I.sub.c 21 of which is then input into the loop filter 20.
The charge pump 18 is an analog element which acts in response to an indication of a phase difference between signals supplied by the reference frequency source oscillator and signals supplied by the voltage controlled oscillator 22. The charge pump 18 generates phase error correction pulses which are supplied to the loop filter 20 and the voltage controlled oscillator 22 to change the frequency of the VCO output signal 16. Conventional charge pump circuits typically contain a current source and a current sink to pull the charge pump 18 output voltage up or down, respectively, by providing appropriate current to a capacitive input of the loop filter 20.
The loop filter 20 smoothes the phase/frequency detector 14 output voltage and determines the loop performance, based upon selected loop filter 20 elements. The output of the loop filter 20 adjusts the voltage of the voltage-controlled oscillator (VCO) 22 and determines the frequency f.sub.out of the output signal 16 of the VCO 22 and the PLL circuit. The output signal 16 of the VCO 22 is then fed back, divided by integer M in the M divider 24, and input into the feedback input of the phase/frequency detector 14. The output voltage of the phase/frequency detector 14 varies according to any change in the phase difference between the output signal 16 of the VCO 22 and the input signal 10.
The PLL circuit produces the output signal 16 whose frequency f.sub.out is equal to the value [(f.sub.ref /R)/N], and the phase of the VCO output signal 16 follows the phase of the input reference signal 10. Therefore, the feedback of the PLL provides a means for locking the phase and frequency f.sub.out of the output signal 16 in accordance with the phase and frequency of the input reference signal 10. If the input reference signal 10 has a highly stable reference frequency, the PLL circuit produces the output signal 16 with a highly stable frequency f.sub.out.
Conventional frequency synthesizers with PLL loops typically obtain frequency division with large division values when they are used to generate RF frequencies from a high-frequency reference source. In a PLL circuit, the PLL gain is determined by multiplying the PFD gain with the VCO gain. In the circuit of FIG. 1, since the VCO 22 gain is usually fixed by the system, only the loop filter 20 elements and the phase/frequency detector 14 gain can provide the PLL designer with the freedom to optimize the PLL behavior and obtain a circuit with high PLL gain. The PFD gain is a function of the charge pump 18 output current I.sub.c 21 and a resistor of the loop filter 20. Therefore, the phase/frequency detector 14 gain is set by the output current I.sub.c 21 of the charge pump 18, when the loop filter 20 resistor value cannot be changed, which limits the designer's flexibility regarding the number of PLL parameters that can be controlled. So, in a conventional PLL circuit, to increase the PFD gain and thus the PLL gain, the magnitude of the current I.sub.c 21 must be increased to meet the requirements.
In the conventional frequency synthesizer-based applications the magnitude of the current input into the charge pump 18 has to be high to meet the requirement for the loop filter 20 and the VCO 22 gain. With this constraint, it can be difficult to design a compact charge pump with low-power and fast switching time. For example, model LMX2330A integer-N frequency synthesizer, manufactured by National Semiconductors, requires a current of 4.5 mA for the charge pump, used in their frequency synthesizer circuit, which makes the charge pump quite large.
Accordingly, there is a need in the art for an improved charge pump-based phase locked loop circuit with high gain, using a low-power small charge pump with fast switching time. There is also a need for a method for enhancing the gain of an improved charge pump-based phase locked loop circuit, while reducing the magnitude of the current input into the charge pump to provide a charge pump circuit with fast operating speed.